?002 fairchild semiconductor corporation RFD8P05, RFD8P05sm, rfp8p05 rev. b RFD8P05, RFD8P05sm, rfp8p05 8a, 50v, 0.300 ohm, p-channel power mosfets these products are p-channel power mosfets manufactured using the megafet process. this process, which uses feature sizes approaching those of lsi circuits, gives optimum utilization of silicon, resulting in outstanding performance. they were designed for use in applications such as switching regulators, switching converters, motor drivers, and relay drivers. these transistors can be operated directly from integrated circuits. formerly developmental type ta09832. features 8a, 50v ? ds(on) = 0.300 ? uis soa rating curve soa is power dissipation limited nanosecond switching speeds linear transfer characteristics high input impedance related literature - tb334 ?uidelines for soldering surface mount components to pc boards symbol packaging ordering information part number package brand RFD8P05 to-251aa d8p05 RFD8P05sm to-252aa d8p05 rfp8p05 to-220ab rfp8p05 note: when ordering, use the entire part number. add the suf? 9a to obtain the to-252aa variant in tape and reel, i.e., RFD8P05sm9a. d g s jedec to-220ab jedec to-251aa jedec to-252aa gate drain (flange) source drain source drain (flange) gate drain gate source drain (flange) data sheet january 2002
?002 fairchild semiconductor corporation RFD8P05, RFD8P05sm, rfp8p05 rev. b absolute maximum ratings t c = 25 o c unless otherwise speci?d RFD8P05, RFD8P05sm, rfp8p05 units drain to source voltage (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . v dss -50 v drain to gate voltage (r gs = 20k ?) (note 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v dgr -50 v continuous drain current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .i d -8 a pulsed drain current (note 3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . i dm -20 a gate to source voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .v gs 20 v maximum power dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . p d 48 w dissipation derating factor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.27 w/ o c single pulse avalanche energy rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . e as see figure 6 operating and storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t j , t stg -55 to 175 o c maximum temperature for soldering leads at 0.063in (1.6mm) from case for 10s. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . t l package body for 10s, see techbrief 334 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .t pkg 300 260 o c o c caution: stresses above those listed in ?bsolute maximum ratings may cause permanent damage to the device. this is a stress o nly rating and operation of the device at these or any other conditions above those indicated in the operational sections of this speci?ation is not implied. note: 1. t j = 25 o c to 150 o c. electrical speci?ations t c = 25 o c unless otherwise speci?d parameter symbol test conditions min typ max units drain to source breakdown voltage bv dss i d = 250 a, v gs = 0v (figure 9) -50 - - v gate threshold voltage v gs(th) v gs = v ds , i d = 250 a (figure 8) -2 - -4 v zero gate voltage drain current i dss v ds = rated bv dss , v gs = 0v - - 1 a v ds = 0.8 x rated bv dss , t j = 150 o c--25 a gate to source leakage current i gss v gs = 20v - - 100 na drain to source on resistance (note 2) r ds(on) i d = 8a, v gs = -10v (figure 7) - - 0.300 ? turn-on time t on v dd = -25v, i d 4a, r g = 9.1 ? , r l = 6.25 ?, v gs = -10v - - 60 ns turn-on delay time t d(on) -16- ns rise time t r -30- ns turn-off delay time t d(off) -42- ns fall time t f -20- ns turn-off time t off - - 100 ns total gate charge q g(tot) v gs = 0 to -20v v dd = -40v, i d = 8a,r l = 5 ?, i g(ref) = -0.3ma - - 80 nc gate charge at -5v q g(-10) v gs = 0 to -10v - - 40 nc threshold gate charge q g(th) v gs = 0 to -2v - - 2 nc thermal resistance junction to case r jc - - 3.125 o c/w thermal resistance junction to ambient r ja to-251aa, to-252aa - - 100 o c/w to-220ab 62.5 o c/w source to drain diode speci?ations t c = 25 o c unless otherwise speci?d parameter symbol test conditions min typ max units source to drain diode voltage (note 2) v sd i sd = -8a - - -1.5 v reverse recovery time t rr i sd = -8a, di sd /dt = 100a/ s - - 125 ns note: 2. pulse test: pulse width 300 s, duty cycle 2%. 3. repetitive rating: pulse width is limited by maximum junction temperature. RFD8P05, RFD8P05sm, rfp8p05
?002 fairchild semiconductor corporation RFD8P05, RFD8P05sm, rfp8p05 rev. b typical performance curves unless otherwise speci?d figure 1. normalized power dissipation vs case temperature figure 2. maximum continuous drain current vs case temperature figure 3. forward bias safe operating area figure 4. unclamped inductive switching capability figure 5. saturation characteristics figure 6. transfer characteristics t c , case temperature ( o c) 25 50 75 100 125 150 175 0 power dissipation multiplier 0 0 0.2 0.4 0.6 0.8 1.0 1.2 -4 -2 0 25 50 75 100 125 150 -8 i d , drain current (a) t c , case temperature ( o c) -10 -6 175 10 1 0.1 -1 -10 -100 v ds , drain to source voltage (v) i d , drain current (a) t c = 25 o c dc operation t j = 175 o c operation in this area is limited by r ds(on) 100 10 1 0.1 1 10 100 t av , time in avalanche (ms) i as , avalanche current (a) starting t j = 150 o c starting t j = 25 o c if r = 0 t av = (l) (i as ) / (1.3 rated bv dss - v dd ) if r 0 t av = (l/r) ln [(i as *r) / (1.3 rated bv dss - v dd ) + 1] i dm 0 0 -2 -4 -6 -10 -8 i d , drain current (a) v ds , drain to source voltage (v) v gs = -6v v gs = -10v -8 v gs = -7v v gs = -5v v gs = -8v -20 -12 -16 -4 pulse duration = 80 s t c = 25 o c v gs = -9v v gs = -4v duty cycle = 0.5% max 0 -6 -9 -12 -15 -3 0 8 175 o c pulse duration = 80 s v dd = 15v i ds(on) , drain to source current (a) v gs , gate to source voltage (v) -55 o c 25 o c 20 16 12 4 duty cycle = 0.5% max RFD8P05, RFD8P05sm, rfp8p05
?002 fairchild semiconductor corporation RFD8P05, RFD8P05sm, rfp8p05 rev. b figure 7. normalized drain to source on resistance vs junction temperature figure 8. normalized gate threshold voltage vs junction temperature figure 9. normalized drain to source breakdown voltage vs junction temperature figure 10. capacitance vs drain to source voltage note: refer to application notes an7254 and an7260. figure 11. normalized switching waveforms for constant gate current typical performance curves unless otherwise speci?d normalized on resistance 3.0 1.0 0.5 0 050 t j , junction temperature ( o c) 150 1.5 100 2.0 2.5 200 -50 pulse duration = 80 s v gs = -10v, i d = -8a duty cycle =0.5% max -50 50 0 100 150 1.50 normalized gate threshold voltage t j , junction temperature ( o c) 200 v gs = v ds , i d = -250 a 1.25 1.00 0.75 0.50 0.25 0 normalized drain to source 2.0 1.0 0.5 0 050 t j , junction temperature ( o c) 100 1.5 breakdown voltage 150 200 i d = -250 a -50 800 600 400 200 0 0 -5 -10 -15 -20 c, capacitance (pf) v ds , drain to source voltage (v) 1000 -25 c iss c rss c oss v gs = 0v, f = 1mhz c iss = c gs + c gd c rss = c gd c oss c ds + c gs -10 -8 -6 -4 -2 0 -12.5 -25 -37.5 -50 0 time ( s) v gs , gate to source voltage (v) v ds , drain to source voltage (v) v dd = bv dss 20 i g(ref) i g(act) 80 i g(ref) i g(act) gate source voltage r l = 6.25 ? i g(ref) = 0.3ma v gs = 10v v dd = bv dss drain to source 0.75bv dss 0.50bv dss 0.25bv dss voltage RFD8P05, RFD8P05sm, rfp8p05
?002 fairchild semiconductor corporation RFD8P05, RFD8P05sm, rfp8p05 rev. b test circuits and waveforms figure 12. unclamped energy test circuit figure 13. unclamped energy waveforms figure 14. switching time test circuit figure 15. resistive switching waveforms figure 16. gate charge test circuit figure 17. gate charge waveforms t p 0.01 ? l i as + - v ds v dd r g dut vary t p to obtain required peak i as 0v v gs v dd v ds bv dss t p i as t av 0 v gs r l r g dut + - v dd t d(on) t r 90% 10% v ds 90% t f t d(off) t off 90% 50% 50% 10% pulse width v gs t on 10% 0 0 r l v gs + - v ds v dd dut i g(ref) v dd q g(th) v gs = -1v q g(-5) v gs = -5v q g(tot) v gs = -10v v ds -v gs i g(ref) 0 0 RFD8P05, RFD8P05sm, rfp8p05
disclaimer fairchild semiconductor reserves the right to make changes without further notice t o any products herein t o improve reliability , function or design. fairchild does not assume any liability arising out of the applica tion or use of any product or circuit described herein; neither does it convey any license under its p a tent rights, nor the rights of others. trademarks the following are registered and unregistered trademarks fairchild semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. life support policy fairchild?s products are not authorized for use as critical components in life support devices or systems without the express written approval of fairchild semiconductor corporation. as used herein: 1. life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, or (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. a critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. product status definitions definition of terms datasheet identification product status definition advance information preliminary no identification needed obsolete this datasheet contains the design specifications for product development. specifications may change in any manner without notice. this datasheet contains preliminary data, and supplementary data will be published at a later date. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains final specifications. fairchild semiconductor reserves the right to make changes at any time without notice in order to improve design. this datasheet contains specifications on a product that has been discontinued by fairchild semiconductor. the datasheet is printed for reference information only. formative or in design first production full production not in production optologic? optoplanar? pacman? pop? power247? powertrench qfet? qs? qt optoelectronics? quiet series? silent switcher fast fastr? frfet? globaloptoisolator? gto? hisec? isoplanar? littlefet? microfet? micropak? microwire? rev. h4 a acex? bottomless? coolfet? crossvolt ? densetrench? dome? ecospark? e 2 cmos tm ensigna tm fact? fact quiet series? smart start? star*power? stealth? supersot?-3 supersot?-6 supersot?-8 syncfet? tinylogic? trutranslation? uhc? ultrafet a a a star*power is used under license vcx?
|
